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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
USE work.MemoryUnit.all;

--see chu page 31

entity PackageExample is
--	port (Clk : in std_logic;
--        add : in integer;
--        wnr : in std_logic;
--        d_i : in std_logic_vector(7 downto 0);
--        d_o : out std_logic_vector(7 downto 0)
--     );
	port( a: in std_logic_vector (2 downto 0);
			even : out std_logic);
end PackageExample;

architecture Behavioral of PackageExample is
	component xor2
		port(i0, i1 : in std_logic;
				O : out std_logic);
	end component;
	
	component buf
		port( i : in std_logic;
				o : out std_logic);
	end component;
	
	signal sig1, sig2 : std_logic;
begin
--	PROCESS
--	BEGIN
--		memElement : Memory
--			PORT MAP (data_i => d_i);
--			
--			
--	END PROCESS;

	unit1: xor2 
		port map (i0 => a(0), i1 => a(1), O => sig1);
		
	unit2: xor2
		port map (i0 => a(2), i1 => sig1, O => sig2);
		
	unit3: buf
		port map (i => sig2, o => even);

end Behavioral;